The Watchdog Timer IP features a dual-stage timeout mechanism to provide early warning and system reset for enhanced fault recovery. With configurable timeout periods, status monitoring, and precision timing, it ensures system stability and reliability, preventing crashes and unintended halts
| Port | Width | Direction | Description |
|---|---|---|---|
| MCLK | 1 | Input | Global input clock |
| rst_n | 1 | Input | Global reset signal |
| sck_in | 1 | Input | Serial clock, used in slave mode |
| ws_in | 1 | Input | Word select clock, used in slave mode |
| sd_in | 1 | Input | Serial data in |
| scan_en | 1 | Input | Scan mode selection signal (DFT Signal) |
| scan_mode | 1 | Input | Scan enable signal (DFT Signal) |
| sck_out | 1 | Output | Serial clock, used in master mode |
| ws_out | 1 | Output | Word select clock, used in master mode |
| sd_out | 1 | Output | Serial data out |
| Generic Bus Interface | 164 | Input/Output | Generic Bus Interface Signals. More details in the design document |
| Port | Width | Direction | Description |
|---|---|---|---|
| MCLK | 1 | Input | Global input clock |
| rst_n | 1 | Input | Global reset signal |
| sck_in | 1 | Input | Serial clock, used in slave mode |
| ws_in | 1 | Input | Word select clock, used in slave mode |
| sd_in | 1 | Input | Serial data in |
| scan_en | 1 | Input | Scan mode selection signal (DFT Signal) |
| scan_ mode |
1 | Input | Scan enable signal (DFT Signal) |
| sck_out | 1 | Output | Serial clock, used in master mode |
| ws_out | 1 | Output | Word select clock, used in master mode |
| sd_out | 1 | Output | Serial data out |
| Generic Bus Interface | 164 | Input/ Output |
Generic Bus Interface Signals. More details in the design document |
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