The USART IP is a versatile, high-speed serial communication module supporting both asynchronous and synchronous modes. With configurable baud rates, FIFO buffering, and hardware flow control, it ensures efficient and reliable
| Port | Width | Direction | Description |
|---|---|---|---|
| clk | 1 | Input | Global Clock Signal |
| rst_n | 1 | Input | Global Reset Signal |
| sclk_i | 1 | Input | Synchronous Mode clock input |
| cs_i | NUM SLAVES | Input | Synchronous Mode chip select input |
| cts | 1 | Input | Clear to send. Used only in Asynchronous Mode |
| rx_i | 1 | Input | Serial data in |
| scan_mode | 1 | Input | Scan mode selection signal (DFT Signal) |
| scan_en | 1 | Input | Scan enable signal (DFT Signal) |
| sclk_o | 1 | Output | Used only in synchronous mode. Output clock when in master mode |
| cs_o | NUM SLAVES | Output | Used in Synchronous Mode. Chip Select Signal in master mode |
| txd | 1 | Output | Serial data out |
| rts | 1 | Output | Ready to send. Used only in Asynchronous Mode |
| Generic Bus Interface | 99 | Input/Output | Generic Bus Interface Signals. More details in the design document |
| DMA Interface | 137 | Input/Output | Generic Bus Interface Signals. More details in the design document |
| Port | Width | Direction | Description |
|---|---|---|---|
| sclk_i | 1 | Input | Used only in synchronous mode. Input clock when in slave mode |
| cs_i | 1 | Input | Used only in synchronous mode. Chip Select in slave mode |
| cts | 1 | Input | Clear to send. Used only in Asynchronous Mode when the hardware flow control mode is enabled |
| rx_i | 1 | Input | Serial data in |
| sclk_o | 1 | Output | Used only in synchronous mode. Output clock when in master mode |
| cs_o | NUM_SLAVES | Output | Used in Synchronous Mode. Chip Select Signal in master mode |
| tx_o | 1 | Output | Serial data out |
| rts | 1 | Output | Ready to send. Used only in Asynchronous Mode when the hardware flow control mode is enabled |
| Port | Width | Direction | Description |
|---|---|---|---|
| clk | 1 | Input | Global Clock Signal |
| rst_n | 1 | Input | Global Reset Signal |
| sclk_i | 1 | Input | Synchronous Mode clock input |
| cs_i | NUM SLAV ES | Input | Synchronous Mode chip select input |
| cts | 1 | Input | Clear to send. Used only in Asynchronous Mode |
| rx_i | 1 | Input | Serial data in |
| scan_ mode | 1 | Input | Scan mode selection signal (DFT Signal) |
| scan_ en | 1 | Input | Scan enable signal (DFT Signal) |
| sclk_o | 1 | Output | Used only in synchronous mode. Output clock when in master mode |
| cs_o | NUM SLAV ES | Output | Used in Synchronous Mode. Chip Select Signal in master mode |
| txd | 1 | Output | Serial data out |
| rts | 1 | Output | Ready to send. Used only in Asynchronous Mode |
| Generic Bus Interface | 99 | Input/ Output | Generic Bus Interface Signals. More details in the design document |
| DMA Interface | 137 | Input /Output | Generic Bus Interface Signals. More details in the design document |
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