Serial Peripheral Interface (SPI)

The SPI IP is a high-performance, flexible serial communication interface designed for seamless data exchange masters and slaves. It supports multi-master/multi-slave configurations, configurable clock phases and polarities, and integrates efficient FIFO buffering for smooth data flow. Optimized for speed and reliability, this design ensures robust connectivity

Sophic silicon Serial Peripheral Interface (SPI) IP

Serial Peripheral Interface (SPI)

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Features

Can be configures in either master or slave mode
Supports both Independent slave and Daisy Chain Configuration in the slave mode
Supports SPI clock and data phase configurations (CPOL, CPHA)
Full-duplex communication for efficient data transfer
Scalable design with configurable data widths and clock rates
Can be connected to DMA through the DMA Interface
Support single master – single slave, single master – multiple slave and multiple master – single slave configurations
Maximum operating frequency is 100 MHz

Diagram

IO Ports

Name	Width	Direction	Description
clk	1	Input	Global clock signal
rst_n	1	Input	Global reset signal
sclk_i	1	Input	Used as input for the clk in slave mode
cs_i	NUM SLAVES	Input	Used as input for chip select in slave mode
rx_i	1	Input	Used for serial data in
scan_mode	1	Input	Scan mode selection signal (DFT Signal)
scan_en	1	Input	Scan enable signal (DFT Signal)
cs_o	NUM SLAVES	Output	Used as output for chip select in master mode
sclk_o	1	Output	Used to output the clk in master mode
txd	1	Output	Used for serial data
Generic Bus Interface	98	Input/Output	Generic Bus Interface Signals. More details in the design document
DMA Interface	137	Input/Output	Generic DMA Interface Signals. More details in the design document

PnR View - 12 nm

IO Ports

Name	Width	Direction	Description
clk	1	Input	Global clock signal
rst_n	1	Input	Global reset signal
sclk_i	1	Input	Used as input for the clk in slave mode
cs_i	NUM SLAVES	Input	Used as input for chip select in slave mode
rx_i	1	Input	Used for serial data in
scan_ mode	1	Input	Scan mode selection signal (DFT Signal)
scan_en	1	Input	Scan enable signal (DFT Signal)
cs_o	NUM SLAVES	Output	Used as output for chip select in master mode
sclk_o	1	Output	Used to output the clk in master mode
txd	1	Output	Used for serial data
Generic Bus Interface	98	Inpu t/Output	Generic Bus Interface Signals. More details in the design document
DMA Interface	137	Input/ Output	Generic DMA Interface Signals. More details in the design document

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Serial Peripheral Interface (SPI)

Sophic silicon Serial Peripheral Interface (SPI) IP

Serial Peripheral Interface (SPI)

Features

Diagram

IO Ports

PnR View - 12 nm

IO Ports

PnR View - 12 nm

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