Joint Test Action Group (JTAG)

The JTAG IP is a powerful, industry-standard interface for seamless test, debug, and programming of digital systems. Featuring a fully compliant TAP controller, instruction decoder, and boundary scan support, it enables efficient fault detection and device configuration

Sophic Silicon JTAG IP Offers

JTAG Brochure

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Features

Implements the IEEE 1149.1 standard Test Access Port (TAP) controller, managing test mode transitions
Supports 9 JTAG instructions, including both mandatory and optional instructions, ensuring compatibility with diverse test and debug scenarios
Allows parameterized instantiation of boundary scan cells to match design requirements
Asserts reset if the TMS signal remains high for 5 consecutive clock cycles, ensuring reliability and fault tolerance
Maximum operating frequency is 50 MHz

Diagram

IO Ports

Port	Width	Direction	Description
tclk	1	Input	Clock Input
tms	1	Input	Mode Select. This controls the FSM
rst_n	1	Input	Reset Signal
ndi	NUM_ CELLS	Input	Normal Data Input
bist_data	32	Input	Data from BIST operation
tdi	1	Input	Serial data in
tdo	1	Output	Serial Data out
highz_en	1	Output	HighZ operation enable signal
bist_en	1	Output	BIST operation enable signal
ndo	NUM_ CELLS	Output	Normal Data Output

PnR View - 12 nm

IO Ports

Port	Width	Direction	Description
tclk	1	Input	Clock Input
tms	1	Input	Mode Select. This controls the FSM
rst_n	1	Input	Reset Signal
ndi	NUM_ CELLS	Input	Normal Data Input
bist_ data	32	Input	Data from BIST operation
tdi	1	Input	Serial data in
tdo	1	Output	Serial Data out
highz _en	1	Output	HighZ operation enable signal
bist_en	1	Output	BIST operation enable signal
ndo	NUM_ CELLS	Output	Normal Data Output

Trusted Silicon and Software design IP partner for Next Generation Wireless, AI & Power Management applications

Joint Test Action Group (JTAG)

Sophic Silicon JTAG IP Offers

JTAG Brochure

Features

Diagram

IO Ports

PnR View - 12 nm

IO Ports

PnR View - 12 nm

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