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Advanced Peripheral Interface (APB) with DMA Interface in Slave Mode

APB (Advanced Peripheral Bus) IP is a reusable intellectual property (IP) block that implements the APB protocol for efficient communication with low power peripherals. It simplifies the integration of devices like UARTs, timers, and GPIOs in SoCs by providing a simple, low latency interface. APB IP ensures compliance with AMBA standards and supports easy interfacing with higher-performance buses like AHB or AXI through bridges.

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APB ( DMA ) Brochure


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    Features

    Diagram

    Interface Signals

    Name Direction Width Description
    PCLKInput1Global clock
    PRESETNInput1Global reset
    PSEL_M/PSEL_S*O & I2Select signal in Master and Slave
    PENABLE_M/PENABLE_S*O & I2Enable signal distinguishes between setup and access phase
    PSTRB_M/PSTRB_S*O & I8Which byte lane of write data is valid during write operation in Master and Slave
    PWAKEUP_M/PWAKEUP_S*O & I2Indicates any activity associated
    PADDR_M/PADDR_S*O & I64Address for write and read in M & S
    PWDATA_M/PWDATA_S*O & I64Write data in Master and Slave
    PRDATA_M/PRDATA_S*I & O64Read data in Master and Slave
    PSLVERR_M/PSLVERR_S*I & O2Indicates slave error when address is out of range in Master and Slave
    PREADY_M/PREADY_S*I & O2Indicates that write and read transaction will perform after it goes high in M & S
    PWRITE_M/PWRITE_S*O & I2Indicates whether write or read has to be performed in Master and Slave
    m_generic bus interfaceO/I8Interface signals to and from the Master
    s_generic bus interfaceO/I8Interface signals to and from the Slave
    DMA interfaceO/I13Interface signals between memory & interconnect

    PnR View - 12 nm

    Interface Signals

    Name Direction Width Description
    PCLKInput1Global clock
    PRESETNInput1Global reset
    PSEL_M
    /PSEL_S*
    O & I2Select signal in Master and Slave
    PENABLE_M
    /PENABLE_S*
    O & I2Enable signal distinguishes between setup and access phase
    PSTRB_M
    /PSTRB_S*
    O & I8Which byte lane of write data is valid during write operation in Master and Slave
    PWAKEUP_M
    /PWAKEUP_S*
    O & I2Indicates any activity associated
    PADDR_M
    /PADDR_S*
    O & I64Address for write and read in M & S
    PWDATA_M
    /PWDATA_S*
    O & I64Write data in Master and Slave
    PRDATA_M
    /PRDATA_S*
    I & O64Read data in Master and Slave
    PSLVERR_M
    /PSLVERR_S*
    I & O2Indicates slave error when address is out of range in Master and Slave
    PREADY_M
    /PREADY_S*
    I & O2Indicates that write and read transaction will perform after it goes high in M & S
    PWRITE_M
    /PWRITE_S*
    O & I2Indicates whether write or read has to be performed in Master and Slave
    m_generic bus interfaceO/I8Interface signals to and from the Master
    s_generic bus interfaceO/I8Interface signals to and from the Slave
    DMA interfaceO/I13Interface signals between memory & interconnect

    PnR View - 12 nm

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