The AXI IP is a high-performance, scalable interface designed for ultra-fast data transfer in modern digital systems. With pipelined architecture, burst transactions, and parallel processing, it ensures low-latency, highbandwidth communication between masters and slaves
| Ports | Width | Direction | Description |
|---|---|---|---|
| ACLK | 1 | Input | Global Clock Signal |
| ARESETN | 1 | Input | Global Reset Signal |
| m_write response | 4 | Input | Write Response Channel (Master) |
| m_read data | 6 | Input | Read Data Channel (Master) |
| s_write address | 8 | Input | Write Address Channel (Slave) |
| s_write data | 5 | Input | Write Data Channel (Slave) |
| s_read address | 8 | Input | Read Address Channel (Slave) |
| m_write address | 8 | Output | Write Address Channel (Master) |
| m_write data | 5 | Output | Write Data Channel (Master) |
| m_read address | 8 | Output | Read Address Channel (Master) |
| s_write response | 4 | Output | Write Response Channel (Slave) |
| s_read data | 6 | Output | Read Data Channel (Slave) |
| m_generic bus interface | 11 | Input/Output | Interface signals to and from the master |
| s_generic bus interface | 9 | Input/Output | Interface signals to and from the slave |
| Ports | Width | Direction | Description |
|---|---|---|---|
| ACLK | 1 | Input | Global Clock Signal |
| ARESETN | 1 | Input | Global Reset Signal |
| m_write response | 4 | Input | Write Response Channel (Master) |
| m_read data | 6 | Input | Read Data Channel (Master) |
| s_write address | 8 | Input | Write Address Channel (Slave) |
| s_write data | 5 | Input | Write Data Channel (Slave) |
| s_read address | 8 | Input | Read Address Channel (Slave) |
| m_write address | 8 | Output | Write Address Channel (Master) |
| m_write data | 5 | Output | Write Data Channel (Master) |
| m_read address | 8 | Output | Read Address Channel (Master) |
| s_write response | 4 | Output | Write Response Channel (Slave) |
| s_read data | 6 | Output | Read Data Channel (Slave) |
| m_generic bus interface | 11 | Input/Output | Interface signals to and from the master |
| s_generic bus interface | 9 | Input/Output | Interface signals to and from the slave |
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